One or more embodiments relate to a method of forming metal wirings of a nonvolatile memory device and, more particularly, to a case wherein the device is a NAND flash memory device.
A flash memory device is a highly integrated non-volatile memory device, which was developed by taking the advantages of Erasable Programmable Read Only Memory (EPROM) and Electrically Erasable Programmable Read Only Memory (EEPROM). The term ‘program’ refers to an operation for writing data into a memory cell, and the term ‘erase’ refers to an operation for erasing data written into a memory cell.
This flash memory device can be divided into two types of flash memory devices, the NOR and the NAND type, each distinguishable by the configuration and operating condition of a cell. Of them, the NAND type flash memory device enables high integration and is widely used in applications requiring high-capacity data retention.
The NAND flash memory device uses a word line, entailing a plurality of memory cell transistors connected in series between a source select line coupled to a common source line and a drain select line coupled to a bit line. A source area is formed in a semiconductor substrate between neighboring source select lines, and a drain area is formed in the semiconductor substrate between neighboring drain select lines. A plurality of peripheral transistors for applying voltage to control gate lines formed in the cell area is formed in a peripheral area of the NAND flash memory device.
The source area, the drain area and the peripheral transistors, are electrically connected to metal wirings formed on the substrate through contact plugs. However, the contact plugs, are typically formed individually through a plurality of subsequent deposition or etch processes. Accordingly, defects are likely in the process of forming the contact plugs.
Typically, a junction area and a gate line are formed by depositing a first insulating layer on a semiconductor substrate. The first insulating layer is etched, thereby forming source contact holes, thus exposing the source area. The source contact plugs are then formed by filling source contact holes with conductive materials, and performing a polishing process such as Chemical Mechanical Polishing (CMP).
Next, a second insulating layer is deposited on the first insulating layer and the source contact plugs. The first insulating layer and the second insulating layer are etched, thereby forming drain contact holes through which the drain area is exposed. The drain contact holes are filled with conductive materials, and a polishing process such as CMP is then performed, thus forming drain contact plugs.
FIG. 1 is a Scanning Electron Microscope (SEM) photograph showing defects occurring in drain contact plugs formed by known methods. As described above, a subsequent deposition and etch processes are performed to form the drain contact plugs. Accordingly, residues B can be generated between the drain contact plugs A. The residuals B can bridge neighboring drain contact plugs A, resulting in deteriorated characteristics of a semiconductor device.